In recent years, there has been known a system-on-a-chip (SOC) comprising a core configured to be continually energized and a core configured such that energization thereof is interrupted during a power-saving mode. For realizing this, it is necessary to provide two DC-DC converters each corresponding to a respective one of the cores to supply DC voltages to the respective cores, individually. In this case, some SOCs can be sought to satisfy a requirement that a voltage difference between the DC voltages to be supplied to the respective cores should be equal to or less than a given threshold.
As a related art 1, there has been known an information processing apparatus designed to improve yield of semiconductor devices. This apparatus comprises a plurality of microprocessors, and a plurality of power supply modules each corresponding to a respective one of the microprocessors, wherein operable upper and lower limit voltages are detected in each of the microprocessors, and a center value between the upper limit voltage and the lower limit voltage is set as an optimal supply voltage to each of the microprocessors.
As a related art 2, there has been known a technique designed to identify a defective semiconductor chip in a manufacturing process of semiconductor chips easily and reliably, and configured such that a fuse and a diode are provided in a circuit of each of the semiconductor chip, wherein after a wafer probe test, the fuse of a defective one of the semiconductor chips is fused to give a defective product identification mark to the defective semiconductor chip.
However, due to a variation in performance of the DC-DC converters, it is difficult to supply the same voltage to each of the cores. Although it is conceivable to employ a DC-DC converter having less variation in performance to thereby allow the voltage difference between the DC voltages to be supplied to the respective cores, to become equal to or less than a given threshold, this measure leads to an increase in cost.
In the related art 1, there is a problem that, in the case where optimal supply voltages to the respective microprocessors have a large difference therebetween, it becomes impossible to allow the voltage difference between the DC voltages to be supplied to the respective cores, to become equal to or less than a given threshold.
The related art 2 addresses the technical problem of facilitating identification of a defective semiconductor chip, without consideration of stable driving of the SOC. Thus, the related art 2 is largely different from the present disclosure in terms of technical problem.
The present disclosure is directed to providing a technique capable of reducing a voltage difference between DC voltages to be supplied, respectively, to two cores, without an increase in cost of a circuit board.